1. Field of the Invention
The present invention relates to the generation of trace elements within a data processing apparatus having one or more components whose behaviour is to be traced.
2. Background of the Invention
Tracing the activity of a data processing system whereby a stream of trace elements is generated including data representing the step-by-step activity within the system is a highly useful tool in system development. However, with the general move towards more deeply embedded processor cores, it becomes more difficult to track the architectural state of the processor core (such as the contents of registers, the values stored at particular memory locations or the status of various buses, paths, lines, flags or modules within processor core or to which the processor core is coupled) via externally accessible pins. Accordingly, as well as off-chip tracing mechanisms for capturing and analysing trace data, increased amounts of tracing functionality are being placed on-chip. An example of such on-chip tracing mechanisms is the Embedded Trace Macrocell (ETM) provided by ARM Limited, Cambridge, England, in association with various of their ARM processors.
Such tracing mechanisms produce in real time a stream of trace elements representing activities of the data processing system that are desired to be traced. This trace stream can then subsequently be used to facilitate debugging of sequences of processing instructions being executed by the data processing system.
It is known to provide tracing mechanisms incorporating trigger points that serve to control the tracing operation, such as starting or stopping tracing upon access to a particular register, memory address, data value. Such mechanisms are very useful for diagnosing specific parts of a system or types of behaviour.
Typically, when the trace is first triggered, the values of all items of architectural state which may need to be reconstructed are traced as a number of trace elements.
Typically, the stream of trace elements that is generated by the ETM is buffered prior to output for subsequent analysis. Such a trace buffer is able to store a finite amount of information and requires a dedicated data bus which has a finite bandwidth over which the elements to be buffered can be received. The trace buffer is generally arranged to store information in a wrap-around manner, i.e. once the trace buffer is full, new data is typically arranged to overwrite the oldest data stored therein. It has been found that the bandwidth of the dedicated data bus limits the rate at which information can be stored in the trace buffer.
Typically, a trace analysing tool is provided which then receives the trace elements from the trace buffer when desired; e.g. once the trace has completed. The trace analysing tool can then reconstruct critical components of the architectural state of the processor core using the stream of trace elements stored in the trace buffer. The trace analysing tool can therefore reconstruct the behaviour of the processor core based on the trace elements.
As data processing systems increase in power and complexity, it is clear that the amount of architectural state and its rate of change will increase. Hence, in order to reliably reconstruct the architectural state it will be appreciated that there is potentially a very large volume of trace elements that need to be traced.
However, there is a problem that there is a finite bandwidth over which the trace elements to be buffered are received and the trace buffer has a finite size. Accordingly, the volume of trace elements that can be buffered, and hence the amount of architectural state that can be reconstructed, is limited.
Hence, it is desired to increase the amount of architectural state that can be reconstructed, given a finite bandwidth over which the trace elements to be buffered are received and a finite size of the trace buffer.